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58 Parallel I/O Models

Table 21. Master Mode Parallel I/O Latency Values for Series 3100 Devices

Symbol Description Minimum Typical Maximum

mrws

R/W~ setup before falling edge of CS~ (See

note 1)

150 ns 3 XIN —

mrwh

R/W~ hold after rising edge of CS~ 100 ns — —

mcspw

CS~ pulse width (See note 1) 150 ns 2 XIN —

mhsh

HS hold after falling edge of CS~ 0 ns — —

mhsv

HS checked by firmware after rising edge of

CS~ (See note 1)

150 ns 10 XIN —

mrdz

Master three-state DATA after rising edge of

R/W~ (See notes 2, 3)

— 0 ns 25 ns

mrds

Read data setup before falling edge of HS

(See note 4)

0 ns — —

mhscs

HS low to falling edge of CS~ (See notes 5, 1) 2 XIN 6 XIN —

mrdh

Read data hold after falling edge of CS~ 0 ns — —

mwdd

Master drive of DATA after falling edge of

R/W~ (See notes 2, 1)

150 ns 2 XIN —

mhsdv

HS low to data valid (See note 5) — 50 ns —

mwds

Write data setup before rising edge of CS~

(See note 1)

150 ns 2 XIN —

mwdh

Write data hold after rising edge of CS~ (See

note 6)

Note 6 — —

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 208 209

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Echelon I/O Model Reference for Smart Transceivers and Neu Manuale Utente Pagina 68

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